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Nonvolatile, I2C Compatible 256-Position, Digital Potentiometer
Preliminary Technical Data
FEATURES
Nonvolatile memoy maintains wiper settings 256-position Compact MSOP-10 (3 mm x 4.9 mm) package I2C(R) compatible interface VLOGIC pin provides increased interface flexibility. End-to-end resistance 5 k, 10 k, 50 k, 100 k Resistance tolerance stored in EEMEM(0.1% accuracy) Power On EEMEM Refresh Time < 1ms Software write protect command Tri-state address decode pins AD0 and AD1 100-year typical data retention at 55C Wide operating temperature -40C to +85C +3V to +5V single-supply
AD5259
parts on one bus, address bits AD0 and AD1 allow up to nine devices on the same bus.
FUNCTIONAL BLOCK DIAGRAMS
VDD VLOGIC DGND 8 DATA SCL SDA
I2C SERIAL INTERFACE
RDAC1
A1 W1 B1
RDAC EEPROM
RDAC1 REGISTER
8 CONTROL
COMMAND DECODE LOGIC
AD0 AD1
ADDRESS DECODE LOGIC
APPLICATIONS
LCD panel VCOM adjustment LCD panel brightness and contrast control Mechanical potentiometer replacement in new designs Programmable power supplies RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment Low resolution DAC replacement Electronics level settings
POWER ON RESET CONTROL LOGIC
Figure 1.
W
1
10 A
AD0 2 AD1 3
AD5259
9B
8 VDD TOP VIEW SDA 4 (Not to Scale) 7 GND 6 VLOGIC SCL 5
GENERAL OVERVIEW
Figure 3. Pinout.
The AD5259 provides a compact nonvolatile 3 mm x 4.9 mm packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution and solid-state reliability. The wiper settings are controllable through an I2C compatible digital interface, which can also be used to read back the wiper register and EEMEM content. Resistor tolerance is also stored within EEMEM and can be used to provide an end-to-end tolerance accuracy of 0.1%. In order to provide added security, command bits are available to place the part into a write protect mode in which data can not be written to the EEMEM register. In addition, a separate VLOGIC pin provides the user with increased interface flexibility. For users who need multiple
Rev. PrJ 7/22/04 | Page 1 of 14
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
Note: The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD5259 TABLE OF CONTENTS
Electrical Characteristics--5 k, 10 k, 50 k, 100 k Versions.............................................................................................. 3 Timing Characteristics--5 k, 10 k, 50 k, 100 k Versions 4 Absolute Maximum Ratings1 .......................................................... 5 Outline Dimensions ....................................................................... 12
Preliminary Technical Data
Ordering Guide .......................................................................... 13 ESD Caution................................................................................ 13
REVISION HISTORY
Revision 0: Initial Version
Vlogic
VDD
EEPROM
AD5259
SCL SDA AD0 AD1
A RDAC REGISTER and LEVEL SHIFTER
I2C SERIAL INTERFACE
COMMAND DECODE LOGIC ADDRESS DECODE LOGIC CONTROL LOGIC
W
GND
B
Figure 3. Block diagram showing level shifters
Rev. PrJ 7/22/04 | Page 2 of 14
AD5259
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS--5 k, 10 k, 50 k, 100 k VERSIONS
(VDD = 5 V 10%, or 3 V 10%; VA = VDD; VB = 0 V; -40C < TA < +85C; unless otherwise noted.) Table 1.
Parameter DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity Resistor Integral Nonlinearity Nominal Resistor Tolerance Resistance Temperature Coefficient Symbol R-DNL R-INL RAB RAB/T Conditions RWB, VA = no connect RWB, VA = no connect TA = 25C VAB = VDD, Wiper = no connect Code = 0x00 Min -1 -2 -30 0.1 0.25 650 50 -1 -1 Code = 0x80 Code = 0xFF Code = 0x00 -3 0 VSS f = 1 MHz, measured to GND, Code = 0x80 f = 1 MHz, measured to GND, Code = 0x80 VA = VB = VDD/2
0.7 x VL -0.5
Max +1 +2 +30
Unit LSB LSB % ppm/C LSB LSB ppm/C LSB LSB V pF pF nA
RWB RWB DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE Differential Nonlinearity DNL Integral Nonlinearity INL Voltage Divider Temperature Coefficient VW/T Full-Scale Error VWFSE Zero-Scale Error VWZSE RESISTOR TERMINALS Voltage Range VA,B,W Capacitance A, B CA,B Capacitance W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Current Input Capacitance POWER SUPPLIES Power Supply Range Positive Supply Current Logic Supply(must match logic levels) Programming Mode Current(EEMEM) Power Dissipation Power Supply Sensitivity DYNAMIC CHARACTERISTICS Bandwidth -3dB Total Harmonic Distortion VW Settling Time (1k/10 k/50 k/100 k) Resistor Noise Voltage Density CW ICM VIH VIL IIL CIL VDD IDD VLOGIC ILOGIC(PROG) PDISS PSS
120 +1 +1 0 3 VDD
0.1 0.3 30 -1 1
45 60 1
VL+0.5 0.3xVL
VIN = 0 V or 5 V 5 2.7 VIH = 5 V or VIL = 0 V 2.7 VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V 10%, Code = Midscale RAB = 5k/ 10 k/50 k/100 k, Code = 0x80 VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VA = 5 V, VB = 0 V, 1 LSB error band RWB = 5 k, RS = 0 35 18 0.02
1
V V A pF V A mA W %/%
5.5 1 VDD 50 0.05
BW THDW tS eN_WB
2000/600/ 100/40 0.1 2 9
kHz % s nV/Hz
Rev. PrJ 7/22/04 | Page 3 of 14
AD5259
Preliminary Technical Data
TIMING CHARACTERISTICS--5 k, 10 k, 50 k, 100 k VERSIONS
(VDD = +5V 10%, or +3V 10%; VA = VDD; VB = 0 V; -40C < TA < +85C; unless otherwise noted.) Table 2.
Parameter Symbol Conditions I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications Apply to All Parts) SCL Clock Frequency fSCL tBUF Bus Free Time between STOP and START t1 tHD;STA Hold Time (Repeated START) t2 After this period, the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time for Repeated START Condition t5 tHD;DAT Data Hold Time t6 tSU;DAT Data Setup Time t7 tF Fall Time of Both SDA and SCL Signals t8 tR Rise Time of Both SDA and SCL Signals t9 tSU;STO Setup Time for STOP Condition t10 Min 0 1.3 0.6 1.3 0.6 0.6 0 100 Typ Max 400 Unit kHz s s s s s s ns ns ns s
0.9 300 300
0.6
SCL
t8
t9
t6
t2
t3 t8 t9
t4
t5
t7
t10
P
S
P
Figure 4. I C Interface Timing Diagram
2
Rev. PrJ 7/22/04 | Page 4 of 14
03842-0-003
SDA
t1
AD5259 I2C INTERFACE
Table 3. Generic Interface Format
S Device Address* (7-bit) Slave Address Byte
Preliminary Technical Data
R/W SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA Instruction Byte Data Byte
P
Table 4. Device Address Lookup* (Note that AD1 and AD0 are tri-state address pins)
Device Address 0011000 0011001 0011010 0101001 0101010 0101011 1001100 1001101 1001110
AD1 0 NC 1 0 NC 1 0 NC 1
AD0 0 0 0 NC NC NC 1 1 1
S = Start Condition P = Stop Condition SA = Slave Acknowledge MA = Master Acknowledge NA = No Acknowledge X = Don't Care W = Write R = Read
Table 5. RDAC-to-EEMEM Interface Command Descriptions C2 0 0 0 1 1 1 C1 0 0 1 0 0 1 C0 0 1 0 0 1 0 Command Description
Operation between I2C and RDAC Operation between I2C and EEPROM Operation between I2C and WP register NOP Restore EEPROM to RDAC Store RDAC to EEPROM
Rev. PrJ 7/22/04 | Page 5 of 14
AD5259
Write Modes
Table 6. Writing to RDAC register
S Device Address* (7-bit) Slave Address Byte 0 SA 0 0 0000 Instruction Byte 0 0
Preliminary Technical Data
SA D7 D6 D5 D4 D3 D2 D1 D0 SA Data Byte
P
Table 7. Writing to EEPROM register
S Device Address* (7-bit) Slave Address Byte 0 SA 0 0 1000 Instruction Byte 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA Data Byte P
Table 8. Activating Software Write Protect
S Device Address* (7-bit) Slave Address Byte 0 SA 0 1 0000 Instruction Byte 0 0 SA 0 0 0 0 0 0 Data Byte 0 WP SA P
Store/Restore Modes
Table 9. Storing RDAC value to EEPROM
S Device Address* (7-bit) 0 SA 1 Slave Address Byte
1 0 0 0 0 0 0 SA P
Instruction Byte
Table 10. Restoring EEPROM to RDAC
S Device Address* (7-bit) 0 SA 1 Slave Address Byte
0 1 0 0 0 0 0 SA P
Instruction Byte
S = Start Condition P = Stop Condition SA = Slave Acknowledge MA = Master Acknowledge NA = No Acknowledge X = Don't Care W = Write R = Read
Rev. PrJ 7/22/04 | Page 6 of 14
AD5259
Preliminary Technical Data
Read Modes
Table 11. Traditional Read back of RDAC Register value
S Device Address* (7-bit) 0 SA 0 Slave Address Byte
0 0 0 0 0 0 0 SA S
Instruction Byte
Device Address* (7-bit) Slave Address Byte
1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Read Back Data
Repeat start Table 12. Traditional Read back of stored EEPROM value
S Device Address* (7-bit) 0 SA 0 Slave Address Byte
0 1 0 0 0 0 0 SA S
Instruction Byte
Device Address* (7-bit) Slave Address Byte
1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Read Back Data
Repeat start Table 13. Traditional Read back of Tolerance i. Consecutively
Device Device Address* Address* D (7-bit) (7-bit) 0 SA 0 0 1 1 1 1 1 0 SA S 1 SA D7 D6 D5 D4 D3 D2 D1 0 MA D7 D6 D5 D4 D3 D2 D1 D0 NA P Sign + Integer Byte Decimal Byte Slave Address Slave Address Instruction Byte Byte Byte
S
Repeat start ii. Individually
Device Device Address* Address* D S (7-bit) (7-bit) 0 SA 0 0 1 1 1 1 1 0 SA S 1 SA D7 D6 D5 D4 D3 D2 D1 0 NA Sign + Integer Byte Slave Address Slave Address Instruction Byte Byte Byte
P
Repeat start
Device Device Address* Address* D S (7-bit) (7-bit) 0 SA 0 0 1 1 1 1 1 1 SA S 1 SA D7 D6 D5 D4 D3 D2 D1 0 NA Decimal Byte Slave Address Slave Address Instruction Byte Byte Byte
P
Repeat start Note: Read modes above are referred to as traditional because the first two bytes for all three cases are "dummy" bytes which function to place the pointer towards the correct register. This is the reason for the Repeat Start. In theory, this step can be avoided if the user is interested in reading a register that was previously written to. For example, if the EEPROM was just written to, then the user can skip the
Rev. PrJ 7/22/04 | Page 7 of 14
AD5259
Preliminary Technical Data
two dummy bytes and proceed directly to the "Slave Address Byte" which would be followed by the "Read Back Data".
Calculating RAB Tolerance Stored in Read-Only Memory
A D7 SIGN D6 26 D5 25 D4 24 D3 23 D2 22 D1 21 D0 20 A D7 2-1 D6 2-2 D5 2-3 D4 2-4 D3 2-5 D2 2-6 D1 2-7 D0 2-8
03823-0-012
A
SIGN
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
Figure 5. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is percent. Only data bytes are shown.)
The AD5259 features a patented RAB tolerance storage in the nonvolatile memory. The tolerance is stored in the memory during factory production and can be read by users at any time. The knowledge of stored tolerance allows users to calculate RAB accurately. This feature is valuable for precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical. The stored tolerance resides in the read-only memory, and is expressed as a percentage. The tolerance is stored in two memory locations in sign magnitude binary form(see Figure 5). The two EEMEM address bytes are 11110(sign+integer) and 11111 (decimal number). The two bytes can be accessed individually in two separate commands(see Table 13ii). Alternatively, in order to allow read back of the first byte followed by the second byte in one command(see Table 13i), the memory pointer will automatically increment from the first to the second EEMEM locations(increments from 11110 to 11111) if read consecutively. In the first memory location, the MSB is designated for the sign (0 = + and 1= -) and the 7 LSBs are designated for the integer portion of the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. For example, if the rated RAB = 10 k and the data readback from Address 11110 shows 0001 1100 and Address 11111 shows 0000 1111, then the tolerance can be calculated as MSB: 0 = + Next 7 MSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 x 2-8 = 0.06 Tolerance = +28.06% and therefore RAB_ACTUAL = 12.806 k
EEMEM Write-Acknowledge Polling
After each write operation to the EEMEM registers, an internal write cycle begins. The I2C interface of the device is disabled. To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition followed by the slave address + the write bit. If the I2C interface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. Other-wise, I2C interface polling can be repeated until it succeeds.
Rev. PrJ 7/22/04 | Page 8 of 14
AD5259
I2C COMPATIBLE 2-WIRE SERIAL BUS
1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 4). The following byte is the Slave Address Byte, which consists of the slave address followed by an R/W bit (this bit determines whether data is read from or written to the slave device). The AD5259 has two tri-state configurable address bits, AD0 and AD1 (see Table 4). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master reads from the slave device. If the R/W bit is low, the master writes to the slave device. 2. Writing: In the write mode, the last bit(R/W) of the Address Byte is logic low. The second byte is the Instruction Byte. The first 3 bits of the Instruction Byte are the command bits(see Table 5). The final 5 bits indicate which EEMEM location the pointer moves to. The user must choose whether to write to the RDAC register, EEMEM register, or activate the software write protect(see Tables 6-8). The final byte is the Data Byte MSB first. In the case of the write protect mode, data is not being stored. Rather, a logic high in the LSB will enable write protect and a logic low will disable write protect. 3. Storing/Restoring: In this mode, only two bytes are necessary; Address and Instruction Bytes. The last bit (R/W) of the Address Byte is logic low. The first 3 bits of the Instruction Byte are the command bits(see Table 5). The two choices are transfer data from RDAC to EEMEM(Store) or from EEMEM to RDAC(Restore). The final 5 bits are all zeros(see Tables 9-10).
Preliminary Technical Data
4. Reading: Assuming the register of interest was not just written to, it is necessary to write a dummy Address and Instruction Byte. The Instruction Byte will vary depending on whether the data that is wanted is the RDAC register, EEMEM register, or Tolerance register(see Tables 11-13). The Tolerance register can be read back consecutively(Table 13i) or individually(Table13ii). Refer to page 8 for detailed information on the interpretation of the tolerance bytes. After the dummy Address and Instruction Bytes are sent, a repeat start is necessary. After the repeat start, another Address Byte is needed except this time, the R/W bit is logic high. Following this Address Byte is the Read Back Byte containing the information requested in the Instruction Byte. After all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a STOP condition (see Figure 6). In read mode, the master issues a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then raises SDA high to establish a STOP condition (see Figure 7).
5.
A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. For example, after the RDAC has acknowledged its Slave Address and Instruction Bytes in the write mode, the RDAC output is updated on each successive byte. If different instructions are needed, the write/read mode has to start again with a new Slave Address, Instruction, and Data Byte. Similarly, a repeated read function of the RDAC is also allowed.
Rev. PrJ 7/22/04 | Page 9 of 14
AD5259 DISPLAY APPLICATIONS
Preliminary Technical Data
Figure 1. VCOM adjustment application assuming that a +5V supply is available. In this case, VDD and VLOGIC would be tied together.
Figure 2. This circuit demonstrates the flexibility of a VLOGIC pin when a separate supply is not available for VDD. VDD can be tapped off the +14.4V where it is resistor divided down to approximately ~5V. VLOGIC can then be taken off the same supply that powers the MCU's logic levels. Now, the 35 mA programming current will be drawn by VLOGIC, and VDD will only draw microamps of supply current used to bias up the internal switches in the digital potentiometer's internal resistor string.
Rev. PrJ 7/22/04 | Page 10 of 14
AD5259 ABSOLUTE MAXIMUM RATINGS1
(TA = +25C, unless otherwise noted.) Table 4
Parameter VDD to GND VA, VB, VW to GND IMAX Pulsed1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance2 JA: MSOP-10 Value -0.3 V to +7 V VSS -0.3V, VDD+0.3V 20 mA 5 mA 0 V to +7 V -40C to +85C 150C -65C to +150C 300C 200C/W
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTES 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX - TA)/JA.
Rev. PrJ 7/22/04 | Page 11 of 14
AD5259 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W 1 10 A
Preliminary Technical Data
AD0 2 AD1 3 SCL 5
AD5259
9B
8 VDD TOP VIEW SDA 4 (Not to Scale) 7 GND 6 VLOGIC
Figure 2. AD5172 Pin Configuration
Table 5. AD5259 Pin Function Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 Mnemonic W ADO AD1 SDA SCL VLOGIC GND VDD B A Description W Terminal. GND VW VDD. Programmable Tri-State Address Bit 0 for Multiple Package Decoding. Programmable Tri-State Address Bit 1 for Multiple Package Decoding. Serial Data Input/Output. Serial Clock Input. Positive edge triggered. Logic power supply. Digital Ground. Positive Power Supply. B Terminal. GND VB VDD. A Terminal. GND VA VDD.
Rev. PrJ 7/22/04 | Page 12 of 14
AD5259
Outline Dimensions
3.00 BSC
Preliminary Technical Data
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 1.10 MAX
0.23 0.20 0.17
SEATING PLANE
8 0
0.80 0.40
COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 3.
10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5259BRMZ51 AD5259BRMZ5-RL71 AD5259BRMZ101 AD5259BRMZ10-RL71 AD5259BRMZ501 AD5259BRMZ50-RL71 AD5259BRMZ1001 AD5259BRMZ100-RL71
1
RAB () 5k 5k 10k 10k 50k 50k 100k 100k
Temperature -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10
Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10
Branding D4P D4P
D4Q D4Q D4R D4R D4S D4S
Z = Pb-free part.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrJ 7/22/04 | Page 13 of 14
AD5259 NOTES
Preliminary Technical Data
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. PR05026-0-7/04(PrJ)
Rev. PrJ 7/22/04 | Page 14 of 14
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